1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device, and more particularly to a process for improving critical dimension uniformity by means of a double exposure and double etching method.
2. Description of the Prior Art
In semiconductor fabrication, lithography is accomplished by subjecting a wafer to step-by-step (or scan-by-scan) exposure. Before exposure, lithography parameters, such as photo-resist coating thickness, baking/cooling temperature and time, developing mechanism and time, exposure dose, best focus offset and numerical aperture (NA), are fine-tuned and optimized. Next, etching is conducted to transfer the photoresist pattern to the underlying layer. The same, before etching, etching parameters, such as gas ratio, flow rate, bias pressure power, temperature, etching selectivity, and etching mode, must be tuned. By means of fine-tuning lithography and etching parameters, the desired critical dimension (CD) can thus be achieved.
However, when after-etching-inspection (AEI) is performed, it is always found that there exists CD bias between wafer center and wafer edge, which results in some fatal failures such as contact hole “open” in wafer acceptance test (WAT). This severely affects yield. Multi-layered films involve more sophisticated and complicate coating and etching steps than conventional single layer film. Therefore, the multi-layered film suffers from a more severe CD bias between wafer center and wafer edge after etching.
CD bias between wafer center and wafer edge mainly results from the following three factors. First of all, multi-layered film formed by spin-on-coating causes inferior uniformity. Referring to FIG. 1, the multi-layered film coated on a semiconductor substrate 12 includes an anti-reflection layer 14, a spin-on glass (SOG) layer 16, and a photoresist layer 18. The topography of the center part 10 and edge part 11 in the multi-layered film is not uniform. The center part 10 is thinner and the edge part 11 is thicker. Second, etching is not uniform for wafer center and wafer edge. Third, the uneven substrate 12 (see FIG. 1) can even cause CD bias.
In the lithography stage, the CD bias between wafer center and wafer edge can be somewhat suppressed by changing parameters of the exposure tool, for example, by changing the ratio of exposure dosage to exposure area. However, in the etching stage, the etch bias still results in CD bias between wafer center and wafer edge, which eventually causes device failure.